NEC PC98 I/O ports (Details)

Reference: PC-9801VX Hardware Manual (1987)

Port address	Details
00xx00000xA00 and 00xx00001xA00	Interrupt controller uPD71059C (Master and Slave) A0 D4 D3 Input operation (Read) 0     IRR, ISR or Interrupt level -> Data bus 1     IMR -> Data bus A0 D4 D3 Output operation (Write) 0 0 0 Data bus -> OCW2 0 0 1 Data bus -> OCW3 0 1 x Data bus -> ICW1 1 x x Data bus -> OCW1,ICW2,ICW3,ICW4 Initialize Command Word Format (ICW1) A0 0   D7 0   D6 0   D5 0   D4 1   D3 LTIM 0:Edge Triggered Input 1:Level Triggered Input D2 ADI CALL Address Interval 0:Interval=8 1:Interval=4 D1 SNGL 0:Not Single 1:Single D0 IC4 0:ICW4 is not required 1:ICW4 is required ICW2 A0 1   D7 T7 Interrupt Vector Address D6 T6 D5 T5 D4 T4 D3 T3 D2 A10   D1 A9   D0 A8   ICW3 (Master Device) A0 1   D7 S7 0:No slave 1:IR Input has a slave D6 S6 D5 S5 D4 S4 D3 S3 D2 S2 D1 S1 D0 S0 ICW3 (Slave Device) A0 1   D7 0   D6 0   D5 0   D4 0   D3 0   D2 ID2 Slave ID D1 ID1 D0 ID0 ICW4 A0 1   D7 0   D6 0   D5 0   D4 SFNM 0:Not Special Fully Nested Mode 1:Special Fully Nested Mode D3 BUF 0x:Non Buffered Mode 10: Buffered Mode (Slave) 11:Buffered Mode (Master) D2 M/S D1 AEOI 0:Normal EOI 1:Auto EOI D0 1   Operation Command Word Format OCW1 A0 1   D7 M7 Interrupt Mask 0:Mask Reset 1:Mask Set D6 M6 D5 M5 D4 M4 D3 M3 D2 M2 D1 M1 D0 M0 OCW2 A0 0   D7 R D7 D6 D5     0 0 1 Non specific EOI command End of interrupt 0 1 1 Specific EOI command 1   1 Rotate on non specific EOI command Automatic rotation 1   0 Rotate in automatic EOI mode (Set) 0 0 0 Rotate in automatic EOI mode (Clear) 1 1 1 Rotate on specific EOI command Specific rotation 1 1 0 Set priority command 0 1 0 No operation D6 SL D5 EOI D4 0   D3 0   D2 L2 IR level to be acted D1 L1 D0 L0 OCW3 A0 0   D7 -   D6 ESMM 00,01:No action 10:Reset special mask 11:Set special mask D5 SMM D4 0   D3 1   D2 P 0:No Poll Command 1:Poll Command D1 RR 00,01: No action 10:Read IRR on next !RD 11:Read ISR on next !RD D0 RIS
00xx0001xxx0	Reserved
00xx000A3A2A1A01	DMA controller uPD8237A-5 A3 A2 A1 A0 Input operation (Read) 0 0 0 0 DMA Channel 0 Current Count Address Read 0 0 0 1 DMA Channel 0 Current Word Count Read 0 0 1 0 DMA Channel 1 Current Count Address Read 0 0 1 1 DMA Channel 1 Current Word Count Read 0 1 0 0 DMA Channel 2 Current Count Address Read 0 1 0 1 DMA Channel 2 Current Word Count Read 0 1 1 0 DMA Channel 3 Current Count Address Read 0 1 1 1 DMA Channel 3 Current Word Count Read 1 0 0 0 DMA Status Register Read 1 1 0 1 DMA Status Temporary Register Read A3 A2 A1 A0 Write operation (Write) 0 0 0 0 DMA Channel 0 Base/Current Address Write 0 0 0 1 DMA Channel 0 Base/Current Word Count Write 0 0 1 0 DMA Channel 1 Base/Current Address Write 0 0 1 1 DMA Channel 1 Base/Current Word Count Write 0 1 0 0 DMA Channel 2 Base/Current Address Write 0 1 0 1 DMA Channel 2 Base/Current Word Count Write 0 1 1 0 DMA Channel 3 Base/Current Address Write 0 1 1 1 DMA Channel 3 Base/Current Word Count Write 1 0 0 0 DMA Command Register Write 1 0 0 1 DMA Request Register Write 1 0 1 0 DMA Single Mask Register Bit Write 1 0 1 1 DMA Mode Register Write 1 1 0 0 DMA Clear Byte Pointer Flip-flop 1 1 0 1 DMA Master Clear 1 1 1 0 DMA Clear Mask Register 1 1 1 1 DMA All Mask Register Bit Write
00xx0010xxx0	Calendar Clock uPD4990A Write Operation (Write) D7 x   D6 x   D5 DI   D4 CLK   D3 STB   D2 C2 Group C2 C1 C0 Function Mode 0 0 0 0 Register Hold DATA OUT=1Hz 0 0 1 Register Shift DATA OUT=LSB=0 or 1 0 1 0 Time Set and Counter Hold DATA OUT=LSB=0 or 1 0 1 1 Time Read DATA OUT=0.5Hz 1 1 0 0 TP=64Hz Set 1 0 1 TP=256Hz Set 1 1 0 TP=2048Hz Set 1 1 1 Extended Mode D1 C1 D0 C0
00xx0010xA1A01	DMA Bank A1 A0 Output operation (Write) 0 0 DMA Channel 2 Bank Write 1 0 DMA Channel 3 Bank Write 1 1 DMA Channel 0 Bank Write
00xx0011xxA00	RS-232C Interface uPD8251A A0 Input operation (Read) 0 Data Read 1 Status Read A0 Output operation (Write) 0 Data Write 1 Mode/Command Write Mode Instruction Format:Asynchronous Mode D7 D6 D5 D4 D3 D2 D1 D0 S2 S1 EP PEN L2 L1 B2 B1 Mode Instruction Format:Synchronous Mode D7 D6 D5 D4 D3 D2 D1 D0 SCS ESD EP PEN L2 L1 0 0 Command Instruction Format D7 EH HUNT Mode D6 IR Request Internal Reset D5 RTS Request Send D4 ER Error Reset D3 SBRX Send Break Character D2 RxE Receiver Enable D1 DTR Data Terminal Ready D0 TxEL Transmitter Enable Status Read Format D7 DSR Data Set Ready D6 SYNDET =pin i/o D5 FE Framing Error D4 OE Overrun Error D3 PE Parity Error D2 TxE =pin i/o D1 RxRDY =pin i/o D0 TxRDY DB Buffer Empty
00xx0011xA1A01	System Port uPD8255A-5 A1 A0 Input operation (Read) 0 0 8255A-5 Port A Switch Read D7 D6 D5 D4 D3 D2 D1 D0 !SW8 !SW7 !SW6 !SW5 !SW4 !SW3 !SW2 !SW1 0 1 8255A-5 Port B Status Read D7 D6 D5 D4 D3 D2 D1 D0 !CI !CS !CD INT3 CRT Type 0 EM CK RTC Read Data A1 A0 Output operation (Write) 1 1 8255A-5 Mode/Controller Word Write Mode Instruction Format D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 0 Control Word Instruction Format D7 0 D6 0 D5 0 D4 0 D3 000:RXRE FLOP 001:TXEE FLOP 010:TXRE FLOP 011:BUZ FLOP 100:MMCKE 110:!PSTBE D2 D1 D0 Bit Set/Reset
00xx0100xA1A00	Printer Interface uPD8255A-5 A1 A0 Input operation (Read) 0 1 8255A-5 Port B Control Read D7 D6 D5 D4 D3 D2 D1 D0 1 0 MOD SW1-3 SW1-8 !BSY 1 0 MOD: 0=10MHz, 1=8MHz SW1-3, SW1-8: 0=ON, 1=OFF A1 A0 Output operation (Write) 0 0 8255A-5 Port A Data Write 1 1 8255A-5 Mode/Controller Word Write Mode Instruction Format D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 1 0 Control Word Instruction Format D7 0 D6 0 D5 0 D4 0 D3 111:!PSTB Signal D2 D1 D0 0:Bit Set 1:Bit Reset
00xx0100A01	Keyboard Interface uPD8251A A0 Input operation (Read) 0 8251A Data Read 1 8251A Status Read Status Read Format D7 -   D6 -   D5 FE Framing Error D4 OE Overrun Error D3 PE Parity Error D2 -   D1 RxRDY =pin i/o D0 -   A0 Output operation (Write) 0 8251A Data Write 1 8251A Mode/Command Write Mode Instruction Format D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 0 Command Instruction Format D7     D6 IR Request Internal Reset D5 RTS Request Send D4 ER Error Reset D3 SBRX Send Break Character D2 RxE Receiver Enable D1 DTR Data Terminal Ready D0 TxEN Transmitter Enable
00xx0110A2A1A00	CRT Controller uPD7220A (Text screen) A2 A1 A0 Input operation (Read) 0 0 0 7220A GDC Status Read 0 0 1 7220A GDC Data Read A2 A1 A0 Output operation (Write) 0 0 0 7220A GDC Parameter Write 0 0 1 7220A GDC Command Write 0 1 0 CRT Interrupt Reset 1 0 0 Mode Flip-flop Control 1 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 MFA2 MFA1 MFA0 MFDT MFA2-0 Name MFDT=1 MFDT=0 000 ATR4(Attr Bit4) Graph Vertical Line 001 Graph Mode Mono Color 010 Column Size 40chrs 80chrs 011 Font Select 7x13 6x8 100 88 Graph Mode 200 lines Others 101 Kanji Access Bitmap Code Access 110 Static Memory Enabled Disabled 111 Allow Display Enabled Disabled 1 0 1 Mode Flop-flop Control 2 D7 ADR6 0000000:Color Select 0000010:Enhanced Mode Others:Reserved D6 ADR5 D5 ADR4 D4 ADR3 D3 ADR2 D2 ADR1 D1 ADR0 D0 DT Color Select 0:8 colors mode 1:16 colors mode Enhanced Mode 0:Compatible Mode 1:Enhanced Mode 1 1 0 Border Color Selection D7 D6 D5 D4 D3 D2 D1 D0 0 G R B 0 0 0 0
00xx0110xxx1	Reserved
00xx0111A2A1A00	CRT Controller A2 A1 A0 Write operation (Write) 0 0 0 Character Position Lines Number Write 0 0 1 Body Face Lines Number Write 0 1 0 Character Lines Number Write 0 1 1 Smooth Scroll Lines Count Write 1 0 0 Scroll Area Above Position Lines Number Write 1 0 1 Scroll Area Lines Number Write 1 1 0 Fast Graphics Mode Register D7 D6 D5 D4 D3 D2 D1 D0 CG mode RMW mode 0 0 !P3EN !P2EN !P1EN !P0EN 1 1 1 Tile Register 0-3
00xx0111xA1A01	Timer Controller uPD8253-5 A1 A0 Input operation (Read) 0 0 8253-5 Counter #0 Read 1 0 8253-5 Counter #2 Read A1 A0 Output operation (Write) 0 0 8253-5 Counter #0 Load 1 0 8253-5 Counter #2 Load 1 1 8253-5 Control Word Write
100000A00	5-inch Fixed Disk Interface A0 Input operation (Read) 0 Interface Data Bus Read 1 Status !RDSW D7 D6 D5 D4 D3 D2 D1 D0 0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 1 REQ ACK BSY MSG C/D I/O - INT9 SW1-8:Dip switches on the interface board A0 Output operation (Write) 0 Interface Data Bus Write 1 Control D7 CHEN Data Bus Out Enable D6 !RDSW Switch status register D5 SEL SEL On/Off D4 0   D3 RST RST On/Off D2 0   D1 DMAE DMA Enable D0 INTE Interrupt Enable
100001A00	Reserved
000110001A1A00	Sound Board A1 A0 Input operation (Read) 0 0 Status Read 0 1 Data Read A1 A0 Output operation (Write) 0 0 Address Write 0 1 Data Write
10001A1A01	Network Interface Board A1 A0 Input operation (Read) 0 0 RAM, Increment Address Count Read D7 D6 D5 D4 D3 D2 D1 D0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0 1 INT Reset(Reset INT by reading) D7 D6 D5 D4 D3 D2 D1 D0 x x x x x x x x 1 0 RAM Read D7 D6 D5 D4 D3 D2 D1 D0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 1 1 Status Read D7 D6 D5 D4 D3 D2 D1 D0 RDY x x ITM x IL2 IL1 x A1 A0 Output operation (Write) 0 0 RAM, Increment Address Count Write D7 D6 D5 D4 D3 D2 D1 D0 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 0 1 Address Count Low Write D7 D6 D5 D4 D3 D2 D1 D0 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 1 0 Vector Strobe D7 D6 D5 D4 D3 D2 D1 D0 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 1 1 Address Counter High Write D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 ITM BA11 BA10 BA9 BA8
1001xA1A00	1MB Floppy Disk Controller uPD765A A1 A0 Input operation (Read) 0 0 765A Status Register Read D7 D6 D5 D4 D3 D2 D1 D0 RQM DIO NDM CB D3B D2B D1B D0B 0 1 765A Data Register Read 1 0 Read Switch D7 0   D6 1   D5 0   D4 0   D3 TYP1 FDD#3/#4 Type 0:1MB,1:1MB/640KB D2 TYP0 FDD#1/#2 Type 0:1MB,1:1MB/640KB D1 0   D0 0   A1 A0 Output operation (Write) 0 1 765A Data Register Write 1 0 Control Register Write Control Register Format (Write) D7 D6 D5 D4 D3 D2 D1 D0 RST RDY 0 1 0 0 0 0
10010A1A01	CMT Interface uPD8251A A1 A0 Input operation (Read) 0 0 8251A Data Read 0 1 8251A Status Read Status Read Format D7 RxD Received Data D6 SYNDET =pin i/o D5 FE Framing Error D4 OE Overrun Error -     D2 TxE =pin i/o D1 RxRDY =pin i/o D0 TxRDY DB Buffer Empty A1 A0 Output operation (Write) 0 0 8251A Data Write 0 1 8251A Mode/Command Write 1 0 Control Register Write Mode Instruction Format D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 1 0 Command Instruction Format D7     D6 IR Request Internal Reset D5     D4 ER Error Reset D3 SBRX Send Break Character D2 RxE Receiver Enable D1     D0 TxEN Transmitter Enable Control Register Format D7 BS Casette MT Baud Rate Select D6 CINH Casette MT Write Data Inhibit D5 CONT Casette MT Motor Control D4 FRQ System Clock Hz Select D3 -   D2 TxEE 8251A TxE Interrupt Enable D1 RxRE 8251A RxRDY Interrupt Enable D0 TxRE 8251A TxRDY Interrupt Enable
100110A01	GP-IB Switch (Input operation) A0 Input operation (Read) 0 Read SW1 on the board D7 D6 D5 D4 D3 D2 D1 D0 GINT1 GINT2 M/S MA4 MA3 MA2 MA1 MA0 1 Read SW1 on the board D7 D6 D5 D4 D3 D2 D1 D0 !IFC GINT2 M/S MA4 MA3 MA2 MA1 MA0
100111x0	Reserved
100111x1	Reserved
00xx1010A2A1A00	CRT Controller uPD7220A (Graph screen) A2 A1 A0 Input operation (Read) 0 0 0 7220A GDC Status Read 0 0 1 7220A GDC Data Read A2 A1 A0 Output operation (Write) 0 0 0 7220A GDC Parameter Write 0 0 1 7220A GDC Command Write 0 1 0 Displaying Access Mode Write D7 D6 D5 D4 D3 D2 D1 D0   0 0 0 0 0 0 0 0 Select plane 0 0 0 0 0 0 0 0 1 Select plane 1 0 1 1 Drawing Access Mode Write D7 D6 D5 D4 D3 D2 D1 D0   0 0 0 0 0 0 0 0 Select plane 0 0 0 0 0 0 0 0 1 Select plane 1 1 0 0 Palette Register 1 0 1 1 1 0 1 1 1
01xx1010A2A1A00	EGC Control A2 A1 A0 Output operation (Write) 0 0 0 Active Plane d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 1 1 1 1 P3 P2 P1 P0 0 0 1 Read Plane d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 FGC BGC 0 0 Read Plane 1 1 1 1 1 1 1 1 0 1 0 Mode Register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 CMP Read Write Source Read Source Register Load ROP Code 0 1 1 If FGC=1 or BGC=1 (Foreground Color) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 FGC 1 0 0 If FGC=1 or BGC=1 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Else d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Mask Register 1 0 1 If FGC=1 or BGC=1 (Background Color) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 BGC 1 1 0 Shifter Control d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 Dir 0 0 0 0 Dest Bit Adr Source Bit Adr 1 1 1 Bit Length d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 Bit Length
00xx1010A2A1A01	Character Pattern ROM A2 A1 A0 Input operation (Read) 1 0 0 Character Pattern Read A2 A1 A0 Output operation (Write) 0 0 0 Character Code Second Byte Write 0 0 1 Character Code First Byte Write 0 1 0 Character Pattern Line Select Counter Write D7 D6 D5 D4 D3 D2 D1 D0 0 0 L/R Row Counter RC4 RC3 RC2 RC1 RC0 RC3-0 L/!R=1 L/!R=0   d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0000   ///             ///       ///       0001     ///     /// /// /// /// /// /// /// /// /// /// /// 0010       ///         ///       ///       0011                                 0100   ///         /// /// /// /// /// /// /// /// ///   0101     ///       ///       ///       ///   0110       ///     ///       ///       ///   0111             /// /// /// /// /// /// /// /// ///   1000                     ///           1001         ///   /// /// /// /// /// /// /// /// ///   1010         ///           ///           1011       ///   /// /// /// /// /// /// /// /// /// /// /// 1100       ///             ///           1101     ///             ///   ///         1110     ///         /// ///       /// ///     1111   ///       /// ///               /// /// RC4:don't care 1 0 0 Character Pattern Write (Users Defined Character)
1011A3A2A1A0	Communication Adapter A3 A2 A1 A0 Input operation (Read) 0 0 0 0 D7201 Channel A Data Read 0 1 0 0 D7201 Channel A Status Read 0 1 1 0 D7201 Channel B Status Read 0 0 0 1 8255A Port A Data Read 0 0 1 1 8255A Port B (DIP switches) Data Read   1 0 1 8255A Port C Data Read D7 D6 D5 D4 D3 D2 D1 D0 MD0 MD1 NRZI !ER DMA TC2 x DR CI 1 0 0 1 8253 Counter#0 Read 1 0 1 1 8253 Counter#1 Read 1 1 0 1 8253 Counter#2 Read A3 A2 A1 A0 Output operation (Write) 0 0 1 0 D7201 Channel B Data Write 0 1 0 0 D7201 Channel A Command Write 0 1 1 0 D7201 Channel B Command Write 0 0 0 1 8255A Port A Data Write D7 D6 D5 D4 D3 D2 D1 D0 INT2 INT1 INT0 DMA TCE DMA TCC DMA M2 DMA M1 DMA M0 0 0 1 1 8255A Port C Data Write D7 D6 D5 D4 D3 D2 D1 D0 MD0 MD1 NRZI !ER x x x x 1 0 0 1 8253 Counter#0 Write 1 0 1 1 8253 Counter#1 Write 1 1 0 1 8253 Counter#2 Write 1 1 1 1 8253 Mode Write D7 D6 D5 D4 D3 D2 D1 D0 SC1 SC0 1 1 0 1 1 1
1011A3A2A1A0	RS-232C Expansion Interface A3 A2 A1 A0 Input operation (Read) 0 0 0 0 Channel 2 Signal Switch Read 0 0 1 0 Channel 3 Signal Switch Read 0 0 0 1 Channel 2 Data Read 1 0 0 1 Channel 3 Data Read 0 0 1 1 Channel 2 Status Read 1 0 1 1 Channel 3 Status Read Signal Switch D7 D6 D5 D4 D3 D2 D1 D0 !CI !CS !CD x x x IR1 IR2 Status D7 D6 D5 D4 D3 D2 D1 D0 DR SYN FE OE PE TE RRDY TRDY A3 A2 A1 A0 Output operation (Write) 0 0 0 0 Channel 2 Mask Set 0 0 1 0 Channel 3 Mask Set 0 0 0 1 Channel 2 Data Write 1 0 0 1 Channel 3 Data Write 0 0 1 1 Channel 2 Mode Command Set 1 0 1 1 Channel 3 Mode Command Set Mask D7 D6 D5 D4 D3 D2 D1 D0 x x x x x TXR TXE RXR Command Set:Asynchronous Mode D7 D6 D5 D4 D3 D2 D1 D0 S2 S1 EP PEN L2 L1 B2 B1 Command Set:Synchronous Mode D7 D6 D5 D4 D3 D2 D1 D0 SCS ESD EP PEN L2 L1 0 0
00xx10111110	1MB/640KB Switch Interface Write Mode Change (Write) D7 0   D6 0   D5 0   D4 0   D3 0   D2 0   D1 FDE 1MB/640KB FDD switching 0:640KB,1:1MB D0 PE I/O port switching 0:640KB,1:1MB Read Mode Status (Read) D7 0   D6 0   D5 0   D4 0   D3 SW3 No.2 Status of Dip switch 3-2 D2 SW3 No.1 Status of Dip switch 3-1 D1 FDE 1MB/640KB FDD switching D0 PE I/O port switching
11000A1A00	Reserved
11001A1A00	640KB Floppy Disk Controller uPD765A A1 A0 Input operation (Read) 0 0 765A Status Register Read D7 D6 D5 D4 D3 D2 D1 D0 RQM DIO NDM CB D3B D2B D1B D0B 0 1 765A Data Register Read 1 0 Read Switch D7 FINT1 00:Expansion Bus INT3 01:Expansion Bus INT4(default) 10:Expansion Bus INT5 11:Expansion Bus INT6 D6 FINT0 D5 1   D4 RDY 0:Not ready, 1:Ready D3 TYP1 FDD#3/#4 Type 0:1MB,1:1MB/640KB D2 TYP0 FDD#1/#2 Type 0:1MB,1:1MB/640KB D1 0   D0 0   A1 A0 Output operation (Write) 0 1 765A Data Register Write 1 0 Control Register Write D7 RST Reset 765A LSI D6 EAI1 00:- 01:Disable attention interrupt 10:- 11:Enable attention interrupt D5 EAI0 D4 DMAE DMA Enable D3 MTON MOTOR On D2 TMSK Motor Control Timer Interrupt Mask D1 x   D0 TTRG Motor Control Timer
1100A2A1A01	GP-IB Interface uPD7210C A2 A1 A0 Input operation (Read) 0 0 0 Data In D7 D6 D5 D4 D3 D2 D1 D0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 0 1 Interrupt Status 1 D7 D6 D5 D4 D3 D2 D1 D0 CPT APT DET END DEC ERR DO DI 0 1 0 Interrupt Status 2 D7 D6 D5 D4 D3 D2 D1 D0 INT SRQ1 LOK REM CO LOKC REMC ADSC 0 1 1 Serial Poll Status D7 D6 D5 D4 D3 D2 D1 D0 S8 PEND S6 S5 S4 S3 S2 S1 1 0 0 Address Status D7 D6 D5 D4 D3 D2 D1 D0 CIC !ATN SPMS LPAS TPAS LA TA MJMN 1 0 1 Command Pass Through D7 D6 D5 D4 D3 D2 D1 D0 CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0 1 1 0 Address 0 D7 D6 D5 D4 D3 D2 D1 D0 x DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0 1 1 1 Address 1 D7 D6 D5 D4 D3 D2 D1 D0 EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1 A2 A1 A0 Output operation (Write) 0 0 0 Byte Out D7 D6 D5 D4 D3 D2 D1 D0 BO7 BO6 BO5 BO4 BO3 BO2 BO1 BO0 0 0 1 Interrupt Mask 1 D7 D6 D5 D4 D3 D2 D1 D0 CPT APT DET END DEC ERR DO DI 0 1 0 Interrupt Mask 2 D7 D6 D5 D4 D3 D2 D1 D0 0 SRQ1 DMAO DMAI CO LOKC REMC ADSC 0 1 1 Serial Poll Status D7 D6 D5 D4 D3 D2 D1 D0 S8 rsv S6 S5 S4 S3 S2 S1 1 0 0 Address Mode D7 D6 D5 D4 D3 D2 D1 D0 ton lon TRM1 TRM0 0 0 ADM1 ADM0 1 0 1 Auxiliary Mode D7 D6 D5 D4 D3 D2 D1 D0 CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0 1 1 0 Address 0/1 D7 D6 D5 D4 D3 D2 D1 D0 ARS DT DL AD5 AD4 AD3 AD2 AD1 1 1 1 End Of String D7 D6 D5 D4 D3 D2 D1 D0 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
1101xxx0	Unused
01111111- 11011A1A01	Mouse Interface uPD8255A-5 A1 A0 Input operation (Read) 0 0 8255A-5 Port A Mouse Data Read D7 D6 D5 D4 D3 D2 D1 D0 LEFT x RIGHT x MD3 MD2 MD1 MD0 A1 A0 Output operation (Write) 1 0 8255A-5 Port C Control Signal Write D7 D6 D5 D4 D3 D2 D1 D0 HC SXY SHL !INT x x x x 1 1 8255A-5 Mode/Control Signal Write 8255A-5 Mode Set D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 1 8255A-5 Control Signal D7 D6 D5 D4 D3 D2 D1 D0 0 x x x 1 0 0 !INT D7 D6 D5 D4 D3 D2 D1 D0 0 x x x 1 1 1 HC
00111111- 11011A011	Timer Controller uPD8253-5 A0 Input operation (Read) 0 Speaker Sound (Beep) Configuration (Timer uPD8253-5 Counter#1 Read/Write) A0 Output operation (Write) A0 Timer uPD8253-5 Control Word Write
10111111- 11011011	Mouse Interrupt Interval Time Configuration (Write) D7 D6 D5 D4 D3 D2 D1 D0   0 0 0 0 0 0 0 0 8ms(120Hz) 0 0 0 0 0 0 0 1 16ms(60Hz) 0 0 0 0 0 0 1 0 34ms(30Hz) 0 0 0 0 0 0 1 1 67ms(15Hz)
00xx11110A1A00	CPU A1 A0 Output operation (Write) 0 0 CPU Reset (only with 80286) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 1 Unmask address bit A20 (Enable protected mode) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0
00xx11111A2A1A0	NDP (80287)

For more details, see (http://www.webtech.co.jp/company/doc/undocumented_mem/)(Japanese).

---

Return to home

Update : 2014/12/02

Copyright(C) 2007-2013, akm. All rights reserved.